False Cache Sharing with Spans
04/18/2020
Introduction
False cache sharing is a leaky abstraction of the CPU cache. CPUs cache memory in cache lines. Typically a cache line is 64 bytes long. That means when a single byte is required from the memory, the CPU rather brings in a full cache line, 64 bytes of data. This is beneficial from spatial/temporal locality principals. CPU cache is usually hierarchical, it has L1, L2 and L3 levels, each different size and speed. L1 and L2 is owned by the actual processor core, while L3 is a shared cache among all CPU cores.
You can find more details on CPU caching and false sharing in Pro .Net Memory Management by Konrak Kokosa.
Lower cache level being owned by the actual CPU cores means that when a data is modified in a cache line, it has to synchronize with other cores sharing the same cache line. This can have a negative performance effect: even in a synchronization free (at application code level) multithreaded application, the CPU cache might become a bottleneck by keeping their cache lines up-to-date.